The present invention relates to a semiconductor power integrated circuit; and, more particularly, to a semiconductor power integrated circuit and a method for fabricating the same having a trench isolation, in which a field oxide layer, a gate oxide layer and a diode insulating layer are simultaneously formed together with a trench filling, thereby reducing processing steps and obtaining a low on-resistance.
Semiconductor power integrated circuits (ICs) for use in a high voltage of 100V to 500V have been used as driver ICs in such as step motors, FED (field emission display) and PDP (plasma display panel). In fabricating the semiconductor power IC having a high breakdown voltage of 30V to 100V, an isolation technology is very important since it directly relates to a packing density and a leakage current.
Referring to FIG. 1, a conventional trench filling technology used for isolation in the semiconductor power device will be described below.
A buried oxide layer 11 and a P-epi (epitaxial) layer 12 are sequentially formed on an N-type silicon substrate 10. A deep P-well region 13 and deep N-well regions 14A and 14B are formed on the P-epi layer 12. Then, an ion implantation is performed to form a P-well region 18, an N-drift region 19, N-well regions 20A and 20B and P-drift regions 21A and 21B. Thereafter, the deep P-well region 13 and the deep N-well regions 14A and 14B are selectively etched to form a trench 15 to thereby expose the buried oxide layer 11.
A TEOS (tetra-ethyl-ortho-silicate)-oxide layer 16 is formed on a whole surface of the semiconductor structure after forming the trench 15 and the polysilicon layer 17 is then formed on the TEOS-oxide layer 16 to thereby fill the trench 15. Then, an etch back or a chemical mechanical polishing (CMP) is performed to planarize a surface of an entire structure after filling the trench 15. Thereafter, a local oxidation of silicon (LOCOS) process is performed at a temperature of about 1000xc2x0 C. for a long time to form a field oxide layer 23, a trench isolation layer 22, a gate oxide layer 24 and a diode insulating layer 25.
Gate electrodes 26 and 27 are formed on the field oxide layer 23 and the gate oxide layer 24. A n+ source regions 28A to 28C, p+ source regions 29A to 29C, n+ drain region 30, and p+ drain regions 31A and 31B are formed on the P-well region 18, the N-drift region 19, the N-well regions 20A and 20B and the P-drift regions 21A and 21B by an ion implantation of impurities.
In semiconductor power IC fabricated by the above-mentioned method, a breakdown voltage and an on-resistance are controlled by the deep N-well regions 14A and 14B and the P-drift regions 21A and 21B, wherein the deep N-well regions 14A and 14B are formed on the P-epi layer 12 having a high resistivity. That is, a breakdown voltage of a vertical direction is determined by a thickness and impurity concentration of the P-epi layer 12 and a depth and impurity concentration of the P-drift regions 21A and 21B. A breakdown voltage of a horizontal direction is determined by a distance between the p+ drain regions 31A and 31B and the p+ source regions 29B and 29C. Additionally, in case where the impurity concentration of the P-drift regions 21A and 21B are low, the voltage breakdown occurs at a drain edge, and in case where the impurity concentration of the P-drift regions 21A and 21B is high, the voltage breakdown occurs at a gate edge.
However, it is difficult to prevent the deep N-well regions 14A and 14B and the N-well regions 20A and 20B from the impurity redistribution since a thermal treatment process is performed at a high temperature for a long time to form the field oxide layer 23, the trench isolation layer 22, the gate oxide layer 24 and the diode insulating layer 25. Therefore, there may occur a problem that the device characteristic is greatly degraded.
It is, therefore, an object of the present invention to provide a semiconductor power integrated circuit and a method for fabricating the same, in which processing steps are reduced and a low on-resistance can be obtained.
In accordance with an embodiment of the present invention, there is provided a method for fabricating a semiconductor power integrated circuit, comprising the steps of: a) forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a channel and a source, and a drift region for forming a drain region; b) forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure; c) forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device; d) forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer; and e) performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern and a gate oxide layer pattern.
In accordance with another embodiment of the present invention, there is provided a semiconductor power integrated circuit, comprising; a) a semiconductor structure having a trench with a predetermined depth from a surface of the semiconductor structure, wherein the semiconductor structure includes an active region having a well region for forming a channel and a source, and a drift region for forming a drain region; b) a trench isolation layer pattern including a first oxide layer and a second oxide layer, wherein the first oxide layer fills inside the trench and has a predetermined thickness from the surface of the semiconductor structure, and wherein the second oxide layer is formed on the first oxide layer and has a predetermined thickness smaller than the second oxide layer; c) a field oxide layer pattern including a third oxide layer and a fourth oxide layer, wherein the third oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the fourth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer; and d) a gate oxide layer pattern including a fifth oxide layer and a sixth oxide layer, wherein the fifth oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the sixth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer.